DocumentCode
780601
Title
Forming Gas Annealing Characteristics of Germanium-on-Insulator Substrates
Author
Jin, Hai-Yan ; Cheung, Nathan W.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA
Volume
29
Issue
7
fYear
2008
fDate
7/1/2008 12:00:00 AM
Firstpage
674
Lastpage
676
Abstract
Large-area layer transfer of germanium-on-insulator (GeOI) substrates has been fabricated by ion-cut processes. Pseudo-MOSFET structure was employed to characterize interface trap density, interface fixed charge density, interface carrier mobility, and bulk carrier mobility of these GeOI substrates with various annealing conditions in forming gas ambient. High-temperature annealing in the vicinity of 500degC-600degC has shown the best carrier mobilities, with the interface trap density and the interface fixed charge density as low as 1010 q/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/( V middots), which is higher than that of silicon [300 cm2/(V middots)] at the same doping concentration level.
Keywords
MOSFET; annealing; carrier mobility; doping profiles; elemental semiconductors; germanium; interface states; semiconductor doping; semiconductor-insulator boundaries; wavelet transforms; Pseudo-MOSFET structure; bulk carrier mobility; doping concentration; gas annealing; germanium-on-insulator substrates; interface carrier mobility; interface fixed charge density; interface trap density; ion-cut processes; large-area layer transfer; temperature 500 degC to 600 degC; Annealing; Dielectric materials; Doping; Germanium; High K dielectric materials; Hysteresis; Plasma temperature; Silicon; Substrates; Wafer bonding; Characterization; forming gas annealing; germanium-on-insulator (GeOI); hysteresis; mobility; pseudo-MOSFET;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2008.2000602
Filename
4558079
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