• DocumentCode
    780617
  • Title

    An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

  • Author

    Baze, M.P. ; Buchner, S. ; Bartholet, W.G. ; Dao, T.A.

  • Author_Institution
    Defence & Space Group, Boeing Aerosp., Seattle, WA, USA
  • Volume
    42
  • Issue
    6
  • fYear
    1995
  • fDate
    12/1/1995 12:00:00 AM
  • Firstpage
    1863
  • Lastpage
    1869
  • Abstract
    A probabilistic description of error propagation in complex circuits is formulated and solved as a set of linear equations. Comparisons are made with experimental data
  • Keywords
    CMOS digital integrated circuits; VLSI; application specific integrated circuits; errors; SEU analysis; complex circuits; digital VLSI CMOS ASICs; error propagation; linear equations; probabilistic theory; Application specific integrated circuits; Circuit simulation; Computer errors; Discrete event simulation; Equations; Error analysis; Fabrication; Logic circuits; Registers; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.489228
  • Filename
    489228
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=780617