Title :
Single clock partial scan
Author :
Cheng, Kwang-Ting Tim
Author_Institution :
California Univ., Santa Barbara, CA, USA
Abstract :
Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits
Keywords :
flip-flops; logic CAD; logic testing; ISCAS89 benchmark circuits; clock-signal routing problems; flip-flop selection; partial-scan designs; scan operation; single clock partial scan; test generation methods; Benchmark testing; Circuit faults; Circuit testing; Clocks; Design automation; Design methodology; Flip-flops; Logic testing; Routing; Sequential analysis;
Journal_Title :
Design & Test of Computers, IEEE
