A novel algorithm for automated optimum design of IIR SC decimators

Author

Ngai, Cheong ; Martins, Rui P. ; Franca, J.E.

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of Macau, China

Volume

49

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

293

Lastpage

296

Abstract

This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched-capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear programming method is adopted for optimum adjustment of the capacitance values, within a specific decimator structure and a finite number of iterations. Several examples of automatic and optimum design of second-order IIR SC decimators are presented, together with a comparison against previous designs, obtained for the same circuits through the use of traditional methods

Keywords

IIR filters; capacitance; circuit CAD; circuit optimisation; iterative methods; linear programming; nonlinear programming; switched capacitor filters; IIR SC decimators; capacitance values; computer-assisted iterative methodology; infinite-impulse response; linear/nonlinear programming method; maximum signal handling capability; minimum capacitance spread; second-order decimators; switched-capacitor decimators; total capacitor area; Algorithm design and analysis; Capacitance; Capacitors; Circuits; Design methodology; Design optimization; Iterative algorithms; Iterative methods; Linear programming; Minimization;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2002.801208

Filename

1017787