A Petri Net Control Unit for High-Speed Modular Signal Processors

This paper proposes a hierarchical representation of digital signal processing algorithms suitable for real-time implementations. Petri net models are used to demonstrate every possible operating parallelism in their graphical expression, the marked Petri graph. Moreover, a hierarchical algorithm execution control based on delayed Petri graphs is presented. A strictly modular system architecture suitable for VLSI implementation and data-driven processing is reviewed in its main components. The algorithm representation is then applied to the design of the control part of the system modules. Details at the logic level of the controllers for an array of digital signal processors are presented as an application of the proposed methodology.