Title :
AVPGEN-A test generator for architecture verification
Author :
Chandra, A. ; Iyengar, V. ; Jameson, D. ; Jawalekar, R. ; Nair, I. ; Rosen, B. ; Mullen, M. ; Yoon, J. ; Armoni, R. ; Geist, D. ; Wolfsthal, Y.
Author_Institution :
IBM Res. Div., Almaden Res. Center, San Jose, CA, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVP´s) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors.<>
Keywords :
VLSI; automatic test software; computer testing; integrated circuit testing; logic testing; microprocessor chips; AVPGEN; S/390 processors; SIGL; architecture verification; biasing techniques; constraint solving; processor design conformance; symbolic execution; symbolic instruction graph language; test generator; user-specified constraints; Computer architecture; Computer bugs; Computer errors; Delay; Logic; Manuals; Natural languages; Process design; Silicon; System testing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
