Title :
Efficient network folding techniques for routing permutations in VLSI
Author :
Alnuweiri, Hussein M. ; Sait, Sadiq M.
Author_Institution :
Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
fDate :
6/1/1995 12:00:00 AM
Abstract :
Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M>
Keywords :
VLSI; circuit layout CAD; digital integrated circuits; integrated circuit interconnections; integrated circuit layout; multiprocessor interconnection networks; network routing; VLSI chips; bit-permute-complement permutations; folded permutation networks; interconnection networks; modular structures; network folding techniques; uniform-size transpose networks; Costs; Degradation; Microelectronics; Multichip modules; Multiprocessor interconnection networks; Packaging; Pins; Routing; Very large scale integration; Wires;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
