Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

Author

Oklobdzija, Vojin G. ; Villeger, David

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

3

Issue

2

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

292

Lastpage

301

Abstract

In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier.<>

Keywords

CMOS logic circuits; digital arithmetic; logic design; multiplying circuits; parallel architectures; CMOS technology; bit reduction techniques; carry propagate adders; column compression tree; multiplier design; optimized final adder; parallel multiplier; uneven signal arrival profile; Adders; CMOS technology; Compressors; Counting circuits; Delay; Design optimization; Logic testing; Signal design; Wiring;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.386228

Filename

386228