A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

In this paper, a VLSI implementation of a complete MIMO channel equalization ASIC based on lattice reduction-aided linear detection is presented. The architecture performs preprocessing steps at channel rate and low-complexity linear data detection at symbol rate. Preprocessing is based on Seysen´s algorithm for lattice reduction. We present algorithmic improvements of the lattice reduction preprocessing in terms of area and throughput of the VLSI implementation with minor impact on the error-rate. Due to the low-complexity implementation of the lattice reduction-aided data detection stage, our architecture is able to achieve very low power in typical packet-based MIMO wireless data transmission scenarios. The final 90 nm CMOS ASIC achieves an energy efficiency for the detection of 24 pJ/bit at a throughput of 720 Mbps with near-optimal error-rate performance.