• DocumentCode
    781902
  • Title

    Performance, wireability, and cooling tradeoffs for planar and 3-D packaging architectures

  • Author

    George, George ; Krusius, J.Peter

  • Author_Institution
    Sch. of Electr. Eng., Cornell Univ., Ithaca, NY, USA
  • Volume
    18
  • Issue
    2
  • fYear
    1995
  • fDate
    5/1/1995 12:00:00 AM
  • Firstpage
    339
  • Lastpage
    345
  • Abstract
    Models for wiring length, cooling, wireability, and signal distribution are derived and integrated into a system-level performance metric used to compare packaging architectures for digital electronic systems. These include the common planar and stack-of-plane structures, in addition to fully 3-D structures with variable aspect ratios. This performance metric has been used to examine optimum packaging architectures for air and water-cooled systems as a function of a number of parameters including the total circuit count. The results show that none of these packaging architectures is always optimal. Rather, the optimum structure is determined by the specific set of system conditions chosen. The reader may easily use this model in order to determine the “best” packaging architecture for system parameters not included in this paper
  • Keywords
    cooling; digital systems; packaging; wiring; 3D packaging architectures; aspect ratios; cooling; digital electronic systems; optimum packaging architectures; planar packaging architectures; signal distribution; stack-of-plane structures; system-level performance metric; total circuit count; wireability; wiring length; Delay; Electronics cooling; Electronics packaging; Fluid flow; Integrated circuit interconnections; Integrated circuit packaging; Logic circuits; Measurement; Silicon; Wiring;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1070-9894
  • Type

    jour

  • DOI
    10.1109/96.386271
  • Filename
    386271