• DocumentCode
    782105
  • Title

    High-frequency, at-speed scan testing

  • Author

    Lin, Xijiang ; Press, Ron ; Rajski, Janusz ; Reuter, Paul ; Rinderknecht, Thomas ; Swanson, Bruce ; Tamarapalli, Nagesh

  • Author_Institution
    Design-for-Test Products Group, Mentor Graphics Corp., Beaverton, OR, USA
  • Volume
    20
  • Issue
    5
  • fYear
    2003
  • Firstpage
    17
  • Lastpage
    25
  • Abstract
    The authors describe new strategies where at-speed scan tests can be applied with internal PLL. They present techniques for optimizing ATPG across multiple clock domains and methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.
  • Keywords
    automatic test pattern generation; boundary scan testing; digital phase locked loops; logic testing; ATGP optimization; at-speed scan tests; delay-test vectors; high-frequency scan testing; internal PLL; multiple clock domains; stuck at faults; test suite; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Clocks; Cost function; Delay; Fault detection; Logic testing; Production;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1232252
  • Filename
    1232252
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=782105