Title :
Embedded deterministic test for low-cost manufacturing
Author :
Rajski, Janusz ; Kassab, Mark ; Mukherjee, Nilanjan ; Tamarapalli, Nagesh ; Tyszer, Jerzy ; Qian, Jun
Abstract :
You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.
Keywords :
automatic test pattern generation; data compression; logic testing; ATPG; BIST; decompression; embedded deterministic test; fault coverage; low-cost manufacturing; on-chip compression; test times; Automatic test pattern generation; Built-in self-test; Costs; Design for testability; Logic design; Logic testing; Manufacturing; Phase shifters; System testing; Test pattern generators;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1232257
