• DocumentCode
    782182
  • Title

    Wafer-package test mix for optimal defect detection and test time savings

  • Author

    Maxwell, Peter C.

  • Volume
    20
  • Issue
    5
  • fYear
    2003
  • Firstpage
    84
  • Lastpage
    89
  • Abstract
    For years, it has been common to run a test at wafer and then exactly the same test again at package. This article shows how one company took a detailed look at the wafer/package test mix and adjusted it to reduce cost while retaining quality.
  • Keywords
    application specific integrated circuits; built-in self test; design for testability; integrated circuit testing; logic testing; ASIC; DFT; cost reduction; optimal defect detection; test time savings; wafer/package test mix; Application specific integrated circuits; Clocks; Costs; Flip-flops; Frequency; Logic testing; Packaging; Production; Vehicles; Wafer scale integration;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1232260
  • Filename
    1232260
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=782182