Title :
Standards - Orthogonality of verilog data types and object kinds
Author_Institution :
Cadence Design Systems
Keywords :
Analog computers; Authorization; Delay; Hardware design languages; Proposals; Registers; Standardization; Standards development; System testing; Wire;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1232262
