DocumentCode

782204

Title

Standards - Orthogonality of verilog data types and object kinds

Author

Lawrence, Jay

Author_Institution

Cadence Design Systems

Volume

20

Issue

5

fYear

2003

Firstpage

94

Lastpage

96

Keywords

Analog computers; Authorization; Delay; Hardware design languages; Proposals; Registers; Standardization; Standards development; System testing; Wire;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2003.1232262

Filename

1232262