• DocumentCode
    782760
  • Title

    High speed regenerator-section terminating LSI operating up to 2.5 Gbit/s using 0.5 μm Si bipolar standard-cell technology

  • Author

    Kawai, K. ; Koike, K. ; Ichino, H. ; Kobayashi, Y.

  • Author_Institution
    NTT LSI Labs., Kanagawa, Japan
  • Volume
    31
  • Issue
    10
  • fYear
    1995
  • fDate
    5/11/1995 12:00:00 AM
  • Firstpage
    791
  • Lastpage
    792
  • Abstract
    A 2.5 Gbit/s 5.6 Kgate LSI for the STM-64 regenerator-section terminator was fabricated using bipolar standard-cell technology for gigabit per second operation. The technology features high performance cell design and LSI layout design based on an accurate timing analysis. The LSI achieves twice the bit rate and half the power dissipation of reported LSIs
  • Keywords
    bipolar digital integrated circuits; cellular arrays; circuit layout CAD; digital communication; elemental semiconductors; large scale integration; optical links; optical repeaters; silicon; synchronous digital hierarchy; timing; 0.5 micron; 2.5 Gbit/s; LSI layout design; SDH protocol; STM-64 regenerator-section terminator; Si; bipolar standard-cell technology; bit rate; cell design; gigabit per second operation; power dissipation; regenerator-section terminating LSI; timing analysis;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950528
  • Filename
    386943
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=782760