Interrupt processing in concurrent processors

Systems architects are faced with many possibilities for designing interrupt processing strategies that optimize computer resources and performance. This framework of hardware implementation techniques highlights choices for consideration. The approach we´ve developed broadly classifies interrupt processing techniques and implementations into six phases. In preparing this taxonomy, we´ve examined the strategies used in 15 modern concurrent processors (those that can process more than one instruction at a time), such as the MIPS R4000 and Intel Pentium. We extend our findings, as applicable, to interrupt processing design decisions in general and survey the different hardware techniques available to designers. We concentrate on concurrent processors because their interrupt processing systems are more complex than those of nonconcurrent processors, and because the level of concurrency in modern processors is steadily increasing