Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications

Author

Kimura, Tohru ; Nakamura, Kazuyuki ; Aimoto, Yoshiharu ; Manabe, Takashi ; Yamashita, Nobuyuki ; Fujita, Yoshihiro ; Okazaki, Shin´ichiro ; Yamashina, Masakazu

Author_Institution

Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan

Volume

30

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

637

Lastpage

643

Abstract

We have fabricated a high yield integrated memory array processor (IMAP) LSI, which features a high memory bandwidth (1.28-GB/s) and low power consumption (4-W max.) and which contains a 2-Mb SRAM with 1.28-I/O´s and 64 processor elements (PE´s) in one chip. A high-bandwidth and low-power memory circuit design is the key technology to realize the IMAP-LSI. We adopted following new designs for memory circuit. (1) Memory access time is designed to be twice as fast as PE execution time (2) Employment of dynamic power control mode, which reduces the memory power consumption down to 30% of maximum power without a loss in access-speed (3) Simplified synchronization with PE´s (4) 4-way block redundancy. These design techniques are suitable for future system integrated ULSI´s

Keywords

large scale integration; microprocessor chips; random-access storage; redundancy; synchronisation; 1.28 GB/s; 2 Mbit; 4 W; IMAP-LSI; PE execution time; SRAM; block redundancy; dynamic power control mode; integrated memory array processor; memory access time; memory bandwidth; memory power consumption; power consumption; synchronization; system integrated ULSIs; Bandwidth; Circuit synthesis; Employment; Energy consumption; Integrated circuit technology; Integrated circuit yield; Large scale integration; Power control; Random access memory; Ultra large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.387066

Filename

387066