Analysis of phase variation of CMOS digital attenuator

A comparison of phase variation and insertion loss between a conventional digital attenuator and a proposed capacitive-phase-compensation digital attenuator design based on an analysis of phase variation is presented. In a standard CMOS technology, the proposed attenuator is analytically demonstrated to have less phase variation than the conventional digital attenuator due to the capacitive-phase-compensation network. The proposed switch can maintain <;1 dB insertion loss while achieving an 8-18° improvement of phase variation than the conventional designs over 10-20 GHz, which support the theoretical analysis.