Experimental characterization of circuits for controlled programming of floating-gate MOSFET´s

This paper presents the results of measurements performed on test structures implementing circuits for controlled erase of floating gate MOSFET´s. The obtained results show that, with cells fabricated using standard technology, the obtained performance is sufficiently good to allow use in analog applications. The circuit has been demonstrated to be robust with respect to variations of the programming pulse characteristics and to partially compensate cell aging effects on the threshold window. This latter feature is particularly interesting for digital applications because it allows the reduction of the window margin, thus improving memory endurance