Title :
Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness
Author :
Lin, Horng-Chih ; Chen, Wei-Chen ; Lin, Chuan-Ding ; Huang, Tiao-Yuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
fDate :
6/1/2009 12:00:00 AM
Abstract :
A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.
Keywords :
nanowires; silicon; transistors; conduction mechanism; double-gated poly-Si nanowire transistor; performance enhancement; polycrystalline silicon; rectangular-shaped NW channel; reduced nanowire channel thickness; Double gate; nanowire (NW); polycrystalline silicon (poly-Si);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2009.2018493
