The cryogenic operation of partially depleted silicon-on-insulator inverters

Author

Simoen, Eddy ; Claeys, Cor

Author_Institution

Interuniversity Micro-Electron. Center, Leuven, Belgium

Volume

42

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

1100

Lastpage

1105

Abstract

This paper describes the cryogenic operation of inverters fabricated in a partially depleted (PD) 1 μm Silicon-on-Insulator (SOI) CMOS technology. As is shown, the floating-body effects like the kink effect degrade the static transfer characteristics considerably. Generally, the effects aggravate upon cooling. Additionally, at deep cryogenic temperatures, e.g., 4.2 K, typical low-temperature anomalies, which are related to the device freeze-out, cause hysteresis effects. Ways for improvement are discussed and compared: As is shown, the PD SOT inverter anomalies can be largely reduced by using the so-called twin-gate configuration

Keywords

CMOS logic circuits; cryogenic electronics; hysteresis; logic gates; silicon-on-insulator; 4.2 K; SOI CMOS technology; Si; cryogenic operation; deep cryogenic temperatures; device freeze-out; floating-body effects; hysteresis effects; kink effect; low-temperature anomalies; partially depleted SOI inverters; static transfer characteristics; twin-gate configuration; CMOS technology; Cryogenics; Helium; Insulation; Inverters; MOSFET circuits; Master-slave; Silicon on insulator technology; Substrates; Temperature;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.387243

Filename

387243