Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation

Author

Ming-Dou Ker ; Yu Wu, Chung

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

42

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

1149

Lastpage

1155

Abstract

For pt. I see ibid., vol. 42, no. 6, p. 1141-48 (1995).The positive-feedback regenerative process in a p-n-p-n structure during CMOS latchup transition has been modeled by a time-varying positive transient pole. The maximum peak value of the positive pole and the time required to first initiate the positive pole are adopted as two useful and meaningful parameters to quantitatively investigate the influence of device parameters on the positive-feedback regeneration of CMOS latchup. Some design guidelines can be obtained to improve latchup immunity of CMOS IC´s,

Keywords

CMOS integrated circuits; fault currents; feedback; integrated circuit modelling; integrated circuit reliability; CMOS IC; CMOS latchup; design guidelines; device parameters; latchup immunity; latchup transition; p-n-p-n structure; positive transient pole method; positive-feedback regenerative process; time-varying positive transient pole; Bipolar transistors; CMOS integrated circuits; CMOS process; Feedback; Guidelines; RNA; Semiconductor device modeling; Space vector pulse width modulation; Thyristors; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.387250

Filename

387250