DocumentCode :
785827
Title :
Sensitivity guided net weighting for placement-driven synthesis
Author :
Ren, Haoxing ; Pan, David Z. ; Kung, David S.
Author_Institution :
IBM Corp., Austin, TX, USA
Volume :
24
Issue :
5
fYear :
2005
fDate :
5/1/2005 12:00:00 AM
Firstpage :
711
Lastpage :
721
Abstract :
Net weighting is a key technique in timing-driven placement (TDP), which plays a crucial role for deep submicron very large scale integration of physical synthesis and timing closure. A popular way to assign net weight is based on its slack, such that the worst negative slack (WNS) of the entire circuit may be minimized. While WNS is an important optimization metric, another figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points, is of equal importance to measure the overall timing closure result for highly complex modern application specific integrated circuits and microprocessor designs. Moreover, to optimally assign net weight for timing closure, the effect of net weighting on timing should be carefully studied. In this paper, we perform a comprehensive analysis of the wirelength, slack, and FOM sensitivities to the net weight, and propose a new net weighting scheme based on those sensitivities. Such sensitivity analysis implicitly takes potential physical synthesis effect into consideration. The experiments on a set of industrial circuits show promising results for both stand-alone TDP and physical synthesis afterwards.
Keywords :
VLSI; application specific integrated circuits; circuit complexity; circuit optimisation; integrated circuit interconnections; integrated circuit layout; sensitivity analysis; ASIC design; FOM sensitivity; VLSI; application specific integrated circuit design; figure of merit; industrial circuits; interconnects; microprocessor design; optimization metric; physical synthesis; placement-driven synthesis; sensitivity analysis; sensitivity guided net weighting; slack threshold; timing closure; timing-driven placement; total slack difference; very large scale integration; wirelength sensitivity; worst negative slack; Application specific integrated circuits; Circuit synthesis; Delay; Design optimization; Integrated circuit interconnections; Integrated circuit measurements; Integrated circuit synthesis; Sensitivity analysis; Timing; Very large scale integration; Interconnect; net weighting; physical synthesis; sensitivity analysis; timing-driven placement (TDP);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.846367
Filename :
1424174
Link To Document :
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