Efficient pipelined CABAC encoding architecture

Context-based adaptive binary arithmetic coding (CABAC) is one of the key techniques adopted in H.264/AVC to achieve much higher compression efficiency than any other existing video compression standards. For its serial and inter-process dependent processing characteristics, the high performance design of CABAC codec is a challenge for hardware implementation. For example, the renormalization and bit-generation steps in encoding architecture are successive processes with variable iteration number which prevents the high throughput of pipelining operation. In this paper, we proposed a fully pipelined design scheme of CABAC encoder based on SoC architecture. With speeding up techniques for pipelining and special but not costly design of renormalization and bit-generation, the proposed design can achieve steady throughput of one symbol/cycle except the slice initialization process.