DocumentCode :
786240
Title :
VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor
Author :
Tsai, Tsung-Han ; Liu, Chun-Nan ; Hung, Jui-Hong
Volume :
54
Issue :
2
fYear :
2008
fDate :
5/1/2008 12:00:00 AM
Firstpage :
933
Lastpage :
939
Abstract :
Audio coding is indispensable in our life and MPEG AAC is one of the most popular audio coding standards. It has been widely used in variant applications. In this paper, we propose VLIW-aware software optimization techniques for the AAC decoding blocks on the parallel architecture core DSP (PACDSP) processor. This approach provides the flexibility for adding new extensions and solves two important issues, low power consumption and limited resources problems on DSP for portable devices. We change the traditional sequential algorithms into parallel processes and minimize the memory utilization of each block. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory .
Keywords :
audio coding; audio equipment; decoding; digital signal processing chips; media streaming; optimisation; parallel architectures; MPEG; VLIW-aware software optimization; advanced audio coding; decoding blocks; frequency 15 MHz; memory size 27 KByte; parallel architecture core DSP processor; parallel processes; power consumption; sequential algorithms; very long instruction word architecture; Application software; Application specific integrated circuits; Audio coding; Decoding; Digital signal processing; Energy consumption; Integrated circuit technology; Parallel architectures; Reduced instruction set computing; Signal processing algorithms;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2008.4560181
Filename :
4560181
Link To Document :
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