A low-power and compact CDMA matched filter based on switched-current technology

Author

Yamasaki, Toshihiko ; Nakayama, Tomoyuki ; Shibata, Tadashi

Author_Institution

Dept. of Frontier Informatics, Univ. of Tokyo, Japan

Volume

40

Issue

4

fYear

2005

fDate

4/1/2005 12:00:00 AM

Firstpage

926

Lastpage

932

Abstract

A low-power and compact code-division multiple-access (CDMA) matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture, which reduced the current flowing in current-memory cells. A low-power clock-on-demand shift register has also been developed. The 256-chip matched filter fabricated in a 0.35-μm technology demonstrated the power dissipation of 1.95 mW at the chip rate of 8 Mchip/s under 2-V power supply. The chip occupies the area of 0.54 mm².

Keywords

MOS integrated circuits; code division multiple access; convertors; low-power electronics; matched filters; shift registers; switched current circuits; 0.35 micron; 1.95 mW; 2 V; clock-on-demand shift register; code-division multiple-access; compact CDMA matched filter; current-memory cells; floating-gate MOS; low-power operation; moderate linear characteristics; neuron MOS; on-chip I-V converters; on-chip V-I converters; sub-block architecture; switched-current technology; CMOS process; CMOS technology; Clocks; Matched filters; Multiaccess communication; Phase modulation; Power dissipation; Power supplies; Shift registers; Voltage; Code-division multiple-access (CDMA); floating-gate MOS; matched filter; neuron MOS; switched-current;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.845561

Filename

1424224