Area-efficient linear regulator with ultra-fast load regulation

Author

Hazucha, Peter ; Karnik, Tanay ; Bloechel, Bradley A. ; Parsons, Colleen ; Finan, David ; Borkar, Shekhar

Author_Institution

Intel Labs., Intel Corp., Hillsboro, OR, USA

Volume

40

Issue

4

fYear

2005

fDate

4/1/2005 12:00:00 AM

Firstpage

933

Lastpage

940

Abstract

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV_P-P output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm² and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm².

Keywords

CMOS integrated circuits; MOS capacitors; MOSFET; microprocessor chips; voltage regulators; 0.2 V; 0.6 nF; 0.9 V; 1.2 V; 100 mA; 54 ns; 90 nm; CMOS technology; MOS capacitor; PMOS pull-up transistor; area-efficient linear regulator; low-dropout regulator; minimum dropout voltage; multisupply voltage microprocessors; on-chip decoupling capacitor; ultra-fast load regulation; ultra-fast single-stage load regulation; CMOS technology; Circuit testing; Circuit topology; Delay; Logic circuits; Low voltage; MOS capacitors; Microprocessors; Regulators; Switching converters; Linear regulator; low-dropout regulator;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.842831

Filename

1424225