Design of hierarchical cellular automata for on-chip test pattern generator

Author

Sikdar, Biplab K. ; Ganguly, Niloy ; Chaudhuri, P. Pal

Author_Institution

Dept. of Comput. Sci. & Technol., Bengal Eng. Coll., Howrah, India

Volume

21

Issue

12

fYear

2002

fDate

12/1/2002 12:00:00 AM

Firstpage

1530

Lastpage

1539

Abstract

This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field GF(2(pqr..)), where each cell of the CA can store and process a symbol in the extension field GF (2(pqr..)). The hierarchical field structure of GF(2(pqr..)) is employed for design of an HCA-based test pattern generator (HCATPG). The HCATPG is ideally suited for testing very large scale integration circuits specified in hierarchical structural description. Experimental results establish the fact that the HCATPG achieves higher fault coverage than that which could be achieved with any other test structures. The concept of percentile improvement in fault coverage is introduced to have a realistic assessment of fault coverage achieved with the proposed RCATPG.

Keywords

Galois fields; automatic test pattern generation; built-in self test; cellular automata; fault diagnosis; integrated circuit testing; logic partitioning; logic testing; BIST; Galois extension field; HCA-based test pattern generator; VLSI circuit testing; fault coverage; hierarchical cellular automata; hierarchical field structure; hierarchical structural description; on-chip test pattern generator; percentile improvement; symbol processing; Arithmetic; Built-in self-test; Circuit faults; Circuit testing; Costs; Linear feedback shift registers; Logic circuits; Pattern analysis; Test pattern generators; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.804380

Filename

1097874