DocumentCode :
787244
Title :
Experimental evidence for nonlucky electron model effect in 0.15-μm NMOSFETs
Author :
Lee, Sang-Gi ; Hwang, Jeong-Mo ; Lee, Hi-Deok
Author_Institution :
Technol. Center, Anam Semicond. Co. Ltd., Kyunggi-Do, South Korea
Volume :
49
Issue :
11
fYear :
2002
fDate :
11/1/2002 12:00:00 AM
Firstpage :
1876
Lastpage :
1881
Abstract :
It is shown that in 0.15-μm NMOSFETs the device lifetime under channel hot-carrier (CHC) stress is lower than that under drain avalanche hot-carrier (DAHC) stress and therefore the hot-carrier stress-induced device degradation in 0.15-μm NMOSFETs cannot be explained in the framework of the lucky electron model (LEM). Our investigation suggests that such a "non-LEM effect" may be due to increased interface state generation by the movement of the maximum impact ionization site from the lightly doped drain (LDD) diffusion region to the boundary of the bulk and LDD region beneath the gate oxide. This paper provides experimental evidence for the non-LEM effect by comparing the degradation characteristics and the maximum impact ionization sites as a function of gate oxide thickness and gate length.
Keywords :
MOSFET; hot carriers; impact ionisation; interface states; semiconductor device reliability; semiconductor device testing; 0.15 micron; NMOSFETs; channel hot-carrier stress; device lifetime; drain avalanche hot-carrier stress; gate length; gate oxide thickness; hot-carrier reliability; hot-carrier stress-induced device degradation; interface state generation; lightly doped drain diffusion region; maximum impact ionization site; nonlucky electron model effect; CMOS technology; Degradation; Drain avalanche hot carrier injection; Electrons; Hot carrier effects; Hot carriers; Impact ionization; MOSFETs; Stress; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2002.804714
Filename :
1097902
Link To Document :
بازگشت