DocumentCode
788046
Title
Silicon compilation of very high level language
Author
Kahrs, Mark
Author_Institution
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Volume
11
Issue
10
fYear
1992
fDate
10/1/1992 12:00:00 AM
Firstpage
1227
Lastpage
1246
Abstract
The design and implementation of a compiler for two very high level languages are addressed. The first language is a set language similar to VERS and SETL. The second language is a novel signal processing language. The compiler uses data flow and type information to constrain possible choices before choosing a possible implementation. Heuristic search is then used to choose from competing concrete implementations of abstract data types. Constraint propagation is used at every selection step to remove incompatible configurations from the search, thereby reducing the search space considerably. A microprogram control store is automatically generated. The output of the compiler is a parts list, a net list of module interconnections, and the fields of the control store
Keywords
circuit layout CAD; high level languages; search problems; SETL; VERS; constraint propagation; data flow graph; heuristic search; microprogram control store; module interconnections; net list; parts list; set language; signal processing language; silicon compilation; very high level language; Application specific integrated circuits; Assembly; Automatic control; Concrete; Helium; High level languages; Integrated circuit interconnections; LAN interconnection; Signal processing; Silicon compiler;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.170987
Filename
170987
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