DocumentCode :
788061
Title :
Numerical study of data retention due to direct tunneling for nonvolatile memory cell
Author :
Watanabe, Hiroshi ; Ishihara, Takamitsu ; Matsunaga, Yasuhiko ; Matsuzawa, Kazuya ; Matsushita, Daisuke ; Muraoka, Kouichi
Author_Institution :
Adv. LSI Technol. Labs., Toshiba Corp., Yokohama, Japan
Volume :
52
Issue :
5
fYear :
2005
fDate :
5/1/2005 12:00:00 AM
Firstpage :
955
Lastpage :
961
Abstract :
A long-term transient device simulation is performed using a nonvolatile memory cell. The reached transient time is over several hundred years. An accuracy of the present simulation is confirmed by obtaining quite good agreements between simulated and measured characteristics of programming and erasing operations and between simulated and measured leakage currents from the floating-gate (FG). It is found that the limitation due to direct tunneling for tunnel oxide thickness is about 3.3-3.4 nm for ten years data retention, whose limitation is not affected by fluctuation due to grain boundaries in the FG of poly-Si.
Keywords :
circuit simulation; grain boundaries; leakage currents; random-access storage; transient analysis; tunnelling; computer-aided analysis; data retention; direct tunneling; floating gate; grain boundaries; leakage currents; nonvolatile memory cell; numerical study; programming/erasing operations; transient analysis; transient device simulation; transient time; tunnel oxide thickness; Capacitance; Current measurement; Degradation; Dielectrics; Electrons; Fluctuations; Leakage current; Nonvolatile memory; Tunneling; Voltage control; Computer-aided analysis; device simulations; direct tunneling; nonvolatile memory; transient analysis;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2005.846312
Filename :
1424385
Link To Document :
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