Leakage power analysis of 25-nm double-gate CMOS devices and circuits

Author

Kim, Keunwoo ; Das, Koushik K. ; Joshi, Rajiv V. ; Chuang, Ching-Te

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

52

Issue

5

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

980

Lastpage

986

Abstract

Leakage power and input pattern dependence of leakage for extremely scaled (L_eff=25nm) double-gate (DG) circuits are analyzed, compared with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications. Unique DG device features resulting from gate-gate coupling are discussed and effectively exploited for optimal low-leakage device design. Design tradeoffs for DG CMOS power and performance are suggested for low-power and high-performance applications. Total power consumptions of static and dynamic circuits and latches for DG device, considering state dependency, show that leakage currents for DG circuits are reduced by a factor of over 10×, compared with bulk-Si counterpart.

Keywords

CMOS integrated circuits; integrated circuit design; leakage currents; low-power electronics; 25 nm; DG CMOS device/circuit; double-gate circuits; drain-induced barrier lowering; dynamic circuits; gate-gate coupling; high-performance applications; latch circuits; leakage currents; leakage power analysis; low-leakage device; low-power applications; numerical simulation; power consumptions; state dependency; static circuits; CMOS technology; Circuit simulation; Circuit synthesis; Coupling circuits; Doping; Energy consumption; Gate leakage; Latches; Leakage current; Numerical simulation; Double-gate (DG) device; drain-induced barrier lowering (DIBL); latch; leakage power;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.846317

Filename

1424389