A surface-potential-based high-voltage compact LDMOS transistor model

In this paper, a surface potential-based compact model is described for high-voltage LDMOS transistors. This model combines the low-voltage MOS region with the high-voltage drift region of an LDMOS transistor. The model includes the effect of the gate extending over the drift region as well as its temperature behavior and geometry scaling. In contrast to subcircuit models, the model has no internal node, since the so-called internal drain voltage is explicitly expressed in terms of the external terminal voltages. By use of an explicit formulation of the surface potential, the dc model thus combines the benefits of short computation times and robustness with accuracy. A comparison with dc measurements shows that the dc model provides an accurate description in all regimes of operation, ranging from subthreshold to super-threshold. In addition, a nodal charge model is derived, to account for the time-dependent behavior of the device. Capacitances obtained from high-frequency measurements show a good agreement with those obtained from the nodal charge model.