Dynamics of integrated vertical DMOS transistors under 100-ns TLP stress

Author

Moens, Peter ; Bychikhin, Sergey ; Reynders, Koen ; Pogany, Dionyz ; Gornik, Erich ; Tack, Marnix

Author_Institution

AMI Semicond. BVBA, Oudenaarde, Belgium

Volume

52

Issue

5

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

1008

Lastpage

1013

Abstract

On-wafer transmission line pulsing (TLP) measurements and transient interferometric mapping experiments on vertically integrated DMOS transistors reveal the presence of hot filament hopping between the two parasitic bipolars. The activity of both intrinsic bipolar transistors is dependent on the TLP current. In addition, a traveling filament along the device width is observed, the traveling speed being estimated to be between 370 and 480 m/s.

Keywords

MOSFET; integrated circuit measurement; semiconductor device reliability; 100 ns; 370 to 480 m/s; TLP stress; current filament; hot filament hopping; hot spot dynamics; integrated vertical DMOS transistors; intrinsic bipolar transistors; on-wafer transmission line pulsing; parasitic bipolars; thermal mapping; transient interferometric mapping; traveling filament; Bipolar transistors; CMOS logic circuits; CMOS process; CMOS technology; Electrostatic discharge; Power system transients; Power transmission lines; Robustness; Silicon; Thermal stresses; Current filament; VDMOS; hot spot dynamics; thermal mapping; transmission line pulsing (TLP) stress;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.846331

Filename

1424393