DocumentCode
788643
Title
Estimating testing effectiveness of the circular self-test path technique
Author
Pilarski, Slawomir ; Krasniewski, Andrzej ; Kameda, Tiko
Author_Institution
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Volume
11
Issue
10
fYear
1992
fDate
10/1/1992 12:00:00 AM
Firstpage
1301
Lastpage
1316
Abstract
The effectiveness of a random built-in self-test technique for VLSI circuits is studied. This technique, called the circular self-test path (CSTP), is applicable to circuits that consist of combinational blocks and registers. In particular, the effectiveness of test pattern generation, the effectiveness of test response compaction and fault coverage are examined. The test generation effectiveness is evaluated by the fraction of all possible test patterns applied during a testing session to the circuit under test. The compaction effectiveness of the CSTP technique is measured by the probability of aliasing, and fault coverage by the fraction of all permanent faults that are detected. For all these measures, simple formulas are developed, which give very accurate estimations without detailed circuit simulation. To demonstrate their accuracy, the estimates obtained by the formulas are compared to the results obtained by extensive simulation experiments
Keywords
VLSI; built-in self test; integrated circuit testing; integrated logic circuits; logic testing; probability; VLSI circuits; aliasing; built-in self-test; circular self-test path technique; combinational blocks; fault coverage; probability; random BIST; test pattern generation; test response compaction; testing effectiveness; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Electrical fault detection; Registers; Test pattern generators; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.170992
Filename
170992
Link To Document