The Design of Derandomizing Buffer Stores for High Data Rates

Derandomizing buffer stores for parallel digital data, and their applicability when the arrival distribution is Poisson, are discussed. It is shown that resolving time rather than size may typically be the major cause of data loss. A logical design for buffer organization is presented which lends itself to high speed operation. The organization is simple, requires only high speed bistable elements and logical gates, and may be used to design derandomizing buffers out of a variety of electronic devices. The highest speed of operation can be closely predicted as the propagation delay of the bistable device plus two times the propagation delay of the gates used. A number of buffers have been constructed using commercially available integrated circuits. One version has been operated at word rates of 114 mHz. Series-parallel organizations are discussed for use in large buffers operated at the highest speeds.