Experimental 128-kbit ferroelectric memory with 1012 endurance and 10-year data retention

An experimental 128-kbit ferroelectric random access memory is presented, which has been designed and fabricated with 0.5 μm ferroelectric storage cell integrated CMOS technology. To achieve stable cell operation, novel design techniques, robust to unstable cell capacitors, are adopted: open bit-line cell array; up-down pulsed plate read/write-back scheme; complementary data preset reference circuitry; and non-ferroelectric reference voltage generator. A self-driven cell plate scheme has also been employed to improve cell array layout efficiency. The prototype chip incorporating these circuit schemes shows 70 ns access time and 120 ns cycle time at 3.3 V and 25°C. The read/write endurance has been confirmed up to 10¹² cycles. It has also been observed that memory cells can retain the data for 10 years