Memory test experiment: industrial results and data

The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different stress combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the fault coverage (FC) of the test algorithms, that the highest FC is obtained at a low voltage level and that the highest detected number of unique faults is obtained at a high voltage level. They also show that the tests with the most promising FC, based on the theory, also tend to have the highest FC in practice. Moreover, the test results show that some algorithms detect faults that cannot be explained with the existing fault models, indicating that the existing fault models still leave much to be explained; for example, no theoretical basis exists to model the stresses and the predicted FC for a given test.