Theory and practice of automatic design constraint generation

Design verification and test generation require the modelling of an environment for circuit under consideration. The task is complex, time consuming and error prone. In dynamic circuits, the presence of multiple clocks makes the problem even worse because of the multiplicity of clocking configurations under which the circuit can be instantiated. A technique is presented, which when provided with a set of user-specified inputs regarding environmental assumptions, can automatically generate all design constraints that can be used as environmental models for verification/test obligations. Experiments on real-life industrial strength circuits show that the technique is effective.