Digital integrator design using Simpson rule and fractional delay filter

The IIR digital integrator is designed by using the Simpson integration rule and fractional delay filter. To improve the design accuracy of a conventional Simpson IIR integrator at high frequency, the sampling interval is reduced from T to 0.5T. As a result, a fractional delay filter needed to be designed in the proposed Simpson integrator. However, this problem can be solved easily by applying well-documented design techniques of the FIR and all-pass fractional delay filters. Several design examples are illustrated to demonstrate the effectiveness of the proposed method.