• DocumentCode
    791576
  • Title

    A method for designing high-radix multiplier-based processing units for multimedia applications

  • Author

    Guevorkian, David ; Launiainen, Aki ; Lappalainen, Ville ; Liuha, Petri ; Punkka, Konsta

  • Author_Institution
    Comput. Archit. Lab., Nokia Res. Center, Tampere, Finland
  • Volume
    15
  • Issue
    5
  • fYear
    2005
  • fDate
    5/1/2005 12:00:00 AM
  • Firstpage
    716
  • Lastpage
    725
  • Abstract
    Multifunctional architecture for video and image processing (MAVIP) to be used in multimedia systems are proposed. MAVIP is a family of reconfigurable architectures derived from a single high-radix (4, 8, or 16) multiplier structure where: a) the list of potential partial products obtained at the first stage of multiplication may be reused; b) pipeline stages may be parallelised at different level to achieve required clock frequency and to improve balancing between these stages; and c) interconnections between the operational blocks may be multiplexed to make the structure multifunctional and to allow reusing basic multiplier blocks. The same device may operate either as a programmable processing unit with digital signal processor-specific operations or as a reconfigurable ASIC. Being small, MAVIP indicates competitive performance in video coding applications.
  • Keywords
    application specific integrated circuits; digital signal processing chips; matrix algebra; mobile communication; multimedia communication; multiplying circuits; pipeline processing; reconfigurable architectures; video coding; digital signal processor; high-radix multiplier-based processing unit; image processing; matrix-vector multiplication; mobile multimedia system; multifunctional architecture; reconfigurable architecture; sum of absolute difference; video processing; Application specific integrated circuits; Clocks; Design methodology; Frequency; Image processing; Multimedia systems; Pipelines; Process design; Reconfigurable architectures; Signal processing; Image and video processing; VLSI; matrix-vector multiplication; media processor; multiplier or multiply-accumulate (MAC); sum of absolute difference (SAD);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems for Video Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1051-8215
  • Type

    jour

  • DOI
    10.1109/TCSVT.2005.846436
  • Filename
    1425535