Title :
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process
Author :
Ker, Ming-Dou ; Chen, Wen-Yi ; Hsu, Kuo-Chun
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ.
Abstract :
A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; low-power electronics; rectifying circuits; 1 V; 130 nm; 2.5 V; 3.3 V; CMOS process; ESD detection circuit; ESD protection circuit; electrostatic discharge circuit; input-output interface; low-voltage devices; nMOS device; pMOS devices; power-rail ESD clamp circuit; substrate-triggered technique; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; MOS devices; Nanoelectronics; Pins; Protection; Voltage; ESD protection circuit; Electrostatic discharge (ESD); high-voltage tolerant; power-rail ESD clamp circuit; substrate-triggered technique;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2006.882818
