• DocumentCode
    791857
  • Title

    Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems

  • Author

    Banerjee, Sati ; Hamada, Takeo ; Chau, Paul M. ; Fellman, Ronald D.

  • Author_Institution
    Gen. Instrum. Corp., San Diego, CA, USA
  • Volume
    43
  • Issue
    6
  • fYear
    1995
  • fDate
    6/1/1995 12:00:00 AM
  • Firstpage
    1468
  • Lastpage
    1484
  • Abstract
    Presents a technique for pipelining heterogeneous multiprocessor systems, macro pipelining based scheduling. The problem can be identified as a combination of optimal task/processor assignment to pipeline stages as well as a scheduling problem. The authors propose a new technique based on iterative applications of partitioning and scheduling schemes whereby the number of pipeline stages are identified and the scheduling problem is solved. The pipeline cycle is optimized in two steps. The first step finds a global coarse solution using the ratio cut partitioning technique. This is subsequently improved by the iterative architecture driven partitioning and the repartitioning and time axis relabeling techniques of the second step. The authors have considered a linear interprocessor communication cost model in scheduling. The proposed technique is applied to several examples. They find that for these examples, the proposed macro pipelining based scheduling can improve the throughput rate several times that of the conventional homogeneous multiprocessor scheduling algorithms
  • Keywords
    iterative methods; pipeline processing; processor scheduling; signal processing; global coarse solution; high performance heterogeneous multiprocessor systems; iterative applications; iterative architecture driven partitioning; linear interprocessor communication cost model; macro pipelining based scheduling; optimal task/processor assignment; pipeline cycle; pipeline stage; ratio cut partitioning technique; repartitioning; time axis relabeling techniques; Costs; Data flow computing; Digital signal processing; Integrated circuit interconnections; Multiprocessing systems; Parallel processing; Pipeline processing; Processor scheduling; Signal processing algorithms; Throughput;
  • fLanguage
    English
  • Journal_Title
    Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1053-587X
  • Type

    jour

  • DOI
    10.1109/78.388859
  • Filename
    388859