Intergate Dielectric Engineering Toward Large P/E Window Planar NAND Flash

The required transition from control gate wraparound to planar structure for NAND flash scaling below 20-nm node causes important loss of coupling factor. In order to recover the program/erase (P/E) window, we develop a novel intergate dielectric (IGD) stack. Simulations identify an ideal three-layer structure that reduces leakage through the IGD and thus improves the memory window at controlled equivalent oxide thickness. A thorough materials investigation allowed to fabricate such three-layer IGD stacks, demonstrating more than 18 V P/E window, good retention, and endurance.