DocumentCode
792831
Title
Nanometer mixed-signal system-on-a-chip design
Author
Chou, Eric Y. ; Sheu, Bing
Volume
18
Issue
4
fYear
2002
fDate
7/1/2002 12:00:00 AM
Firstpage
7
Lastpage
17
Abstract
A mixed-signal system-on-a-chip (SoC) design methodology and the supporting CAD tools are presented. A known tools set is identified for illustration purposes and some alternative tools can equally accomplish the task.
Keywords
circuit layout CAD; design for testability; hardware-software codesign; integrated circuit layout; mixed analogue-digital integrated circuits; product development; CAD tools; R&D prototype stage; behavioral model; bit-true model; design methodology; design tools; floating point system model; front-end design flow; functional model; integrated-circuit design; layout optimization; mixed-signal system-on-a-chip design; nanometer system-on-a-chip; planning stage; product development stage; signal integrity effects; testability; top-down design; Circuit testing; Design automation; Design engineering; Design methodology; Integrated circuit modeling; Integrated circuit testing; Prototypes; Research and development; System testing; System-on-a-chip;
fLanguage
English
Journal_Title
Circuits and Devices Magazine, IEEE
Publisher
ieee
ISSN
8755-3996
Type
jour
DOI
10.1109/MCD.2002.1021118
Filename
1021118
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