Bonded planar double-metal-gate NMOS transistors down to 10 nm

Author

Vinet, M. ; Poiroux, T. ; Widiez, J. ; Lolivier, J. ; Previtali, B. ; Vizioz, C. ; Guillaumot, B. ; Tiec, Y. Le ; Besson, P. ; Biasse, B. ; Allain, F. ; Cassé, M. ; Lafond, D. ; Hartmann, J. -M ; Morand, Y. ; Chiaroni, J. ; Deleonibus, S.

Author_Institution

CEA/DRT-LETI, Grenoble, France

Volume

26

Issue

5

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

317

Lastpage

319

Abstract

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

Keywords

MOSFET; etching; nanoelectronics; silicon-on-insulator; wafer bonding; 10 nm; SOI; access resistance; carrier transport properties; double-metal-gate NMOS transistors; electrical characterization; metal-gate etching; nano-MOSFET; saturation current; self-aligned transfer; short-channel effects control; silicon-on-insulator; wafer bonding; Dry etching; MOSFETs; Nickel; Semiconductor films; Silicon; Substrates; Threshold voltage; Tin; Wafer bonding; Wet etching; Double gate; MOS transistors; electrical characterization; metal gate; nano-MOSFETs silicon-on-insulator (SOI); wafer bonding;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2005.846580

Filename

1425694