Title :
Characterization and design of GaAs SCFL latched comparators based on improved linearized models
Author :
Feng, Shen ; Seitzer, Dieter
Author_Institution :
Fraunhofer Inst. for Integrated Circuits, Erlangen, Germany
fDate :
6/1/1995 12:00:00 AM
Abstract :
This brief presents characterization and design considerations of high-speed and high-precision GaAs latched comparators consisting of source coupled FET logic (SCFL) flip flops. In order to characterize the comparators, linearized equivalent circuit models are improved for the SCFL flip flops. Based on the models, critical design parameters such as recovery time, regeneration time and input voltage sensitivity are determined for the comparators. Circuit configurations for increasing circuit speed and accuracy are characterized and compared. One comparator is optimized and implemented in a 0.5 μm GaAs E/D HEMT technology. Measurement results demonstrate the implemented comparator achieves an average voltage sensitivity of 11.5 mV at low frequencies and an optimal voltage sensitivity of 10.0 mV at an input signal frequency of 2 GHz and a clock frequency of 4 GHz. Predicted voltage sensitivities are also verified to be in good agreement with the measured results
Keywords :
HEMT integrated circuits; III-V semiconductors; comparators (circuits); equivalent circuits; field effect logic circuits; flip-flops; gallium arsenide; logic CAD; sequential circuits; 0.5 micron; 10.0 mV; 11.5 mV; 2 GHz; 4 GHz; E/D HEMT technology; GaAs; SCFL latched comparators; circuit speed; clock frequency; critical design parameters; equivalent circuit models; flip flops; input signal frequency; input voltage sensitivity; linearized models; recovery time; regeneration time; source coupled FET logic; Clocks; Computational modeling; Coupling circuits; Equivalent circuits; FETs; Frequency; Gallium arsenide; Latches; Predictive models; Voltage;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
