Partial SOI type isolation for improvement of DRAM cell transistor characteristics

Author

Lee, Myoung Jin ; Cho, Jun Hee ; Lee, Sang Don ; Ahn, Jin Hong ; Kim, Jin Woong ; Sung Wook Park ; Park, Young June ; Min, Hong Shick

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

26

Issue

5

fYear

2005

fDate

5/1/2005 12:00:00 AM

Firstpage

332

Lastpage

334

Abstract

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.

Keywords

DRAM chips; etching; silicon-on-insulator; DRAM cell transistor; asymmetrical characteristics; body-bias control; buried oxide; drain-induced barrier lowering; isotropic etching; partial SOI type isolation; short-channel effect; silicon-on-insulator; storage node; Analytical models; Dry etching; Epitaxial growth; Fabrication; Random access memory; Silicon on insulator technology; Space technology; Thickness control; Threshold voltage; Voltage control; Buried oxide (BOX); drain-induced barrier lowering (DIBL); short-channel effect (SCE); silicon-on-insulator (SOI);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2005.846590

Filename

1425699