Title :
ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-μm channel length CMOS technologies
Author :
Voldman, Steven H.
Author_Institution :
IBM Microelectronics Div., Essex Junction, VT, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture is discussed. ESD robustness in shallow trench isolation 0.50- and 0.25-μm channel-length CMOS technologies is demonstrated using novel ESD structures
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit technology; isolation technology; protection; 0.25 micron; 0.5 micron; CMOS technologies; ESD protection; ESD robustness; ESD structures; channel length; internal multiple power bus architecture; mixed-voltage interface; multirail disconnected power grid environment; shallow trench isolation; CMOS technology; Circuit noise; Electrostatic discharge; Energy consumption; Integrated circuit technology; Isolation technology; MOSFET circuits; Power grids; Protection; Voltage;
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on
