Design and implantation of an ASIC architecture for 1.6 kbps speech synthesis

In recent years, digital speech processing techniques have made revolutionary advances. One of the techniques that has lead to the improvement of voice-controlled toys, multimedia sound effects, and mobile, including satellite, phones is low-bit-rate speech coding. We present an ASIC architecture for speech synthesis at 1.6 kbps. The processing algorithm is formulated from the hardware-oriented viewpoint. Based on the proposed speech synthesizer, the developed architecture consumes fewer hardware resources but still attains satisfactory quality. It is therefore suitable for hardware implementation.